Journal of Innovation in Electronics and Communication Engineering
  • Year: 2015
  • Volume: 5
  • Issue: 2

Area-Delay-Power Efficient Booth Encoded Reversible Multiplier Using Compressors

  • Author:
  • G. Sree Lakshmi1, Kaleem Fatima2, B.K. Madhavi3
  • Total Page Count: 4
  • Page Number: 47 to 50

1Department of Electronics and Communication Engineering, Geethanjali College of Engineering and Technology, Hyderabad, Telangana, India. gantisiriphd@gmail.com

2Department of Electronics and Communication Engineering, Muffakamjah College of Engineering and Technology, Hyderabad, Telangana, India. kaleemfatima@gmail.com

3Department of Electronics and Communication Engineering, Sridevi Womens College of Engineering and Technology, Hyderabad, Telangana, India. bkmadhavi2009@gmail.com

Online published on 27 June, 2017.

Abstract

Reversible logic gates became very important and promising technology having more applications in low power CMOS design, Quantum computing, Optical computing and Nano Technology. The basic set of gates like AND, OR, XOR are not reversible. A set of reversible gates has been introduced by various researchers. Few basic reversible gates are Feynman, Toffoli, TSG, Fredkin, Peres etc. Theoretically it has been proved that energy dissipation would not occur if a computation is carried out in a reversible way. This paper proposes a Novel reversible Radix 4 Booth Encoded Wallace Tree multiplier using 4:2 compressors, 5:2 compressors.

Keywords

Reversible gates, Compressors, Low power, Booth Encoder