Ultra low power Tri-CAM designs for high speed processors

In the recent emerging fields, the major design constraints are power, area, and performance. With the increase of computational complexity in mobile and computing applications, speed and power become more weight. In this paper, to improve the speed of the processors SRAMs are replaced with the CAMs, to enhance speed further ternary CAM is preferred in the place of bi CAM and owing to the WLOTC structure with the 10-transistor tag cell for accommodating the one-step hit/miss, a small hit access time. Ultra low power concept is applied in this implementation at 45nm CMOS technology to achieve low power and good expansion capability without sacrificing speed. Here, CADENCE VIRTUSO tools were used for experimental verifications.