Implementation of a High Speed Reliable Multiplier using Adaptive Hold Technique

Digital Multipliers play an important role in today's digital signal processing and various other applications. As the rapid developments in technology required, many researchers are going to design multipliers which offer either of the following design targets, high speed, low power consumption. Digital multipliers are among the most critical arithmetic functional units. The overall performance of these systems depends on the throughput of the multiplier. The negative bias temperature instability effect occurs when a pMOS transistor is under negative bias (Vgs = −Vdd), which results the increase in the threshold voltage of the pMOS transistor, hence the delay in the multiplier is increased. In the same way, positive bias temperature instability, occurs when an nMOS transistor is under positive bias. Both the temperature effects decreases the transistor speed, in the long run, the system may fail due to timing violations. Therefore, it is important to design reliable high-performance multipliers. In this paper Design of Multiplier circuit using Adaptive Hold Technique is proposed. By using AHT circuit we can reduce the NBTI & PBTI effects, hence performance in terms of delay will be increased and power consumption can be reduced.