Design of low voltage and power efficient double tail comparator

High speed dynamic regenerative comparators are used in low power and area efficient analog to digital converters to improve speed and power efficiency. Speed and power consumption are the two factors that can define the comparators accuracy. In this paper, a new double tail comparator is proposed by modifying the low voltage low power double tail comparator circuit for power efficient and high speed operation. In the Proposed dynamic Double tail comparator System both the power dissipation and delay time will be significantly reduced. By reducing clock overhead in the double tail comparatordelay and area can be reduced. The circuits presented in this paper are designed in 130nm technology by using mentor graphics tools with asupply voltage of 0.8v and 0.6v. Proposed comparator is compared with existing double tail comparator and the results are discussed in detail.