1Dept. of Electronics and Communication, Rashtreeya Vidyalaya College of Engineering, Bengaluru, Karnataka, India
2Intel Technologies India Private Limited, Bengaluru, Karnataka, India
*Email: linumonthomas479@gmail.com
Online published on 31 March, 2018.
Power reduction is of significant importance in VLSI designs. As VLSI technology goes further in nanometer technology, as speed increases powerbecomes an important parameter. There are various design techniques which can be used to reduce power. Optimization in synthesis and physical design stages can give significant power reduction. In this paper, power reduction through optimization of clock network indigital circuits is discussed.
Low power deisgn, low power Synthesis, VLSI design, Clock network optimization
