Department of Electronics and Communication, Rashtreeya Vidyalaya College of Engineering. Bengaluru, Karnataka, India
Online published on 31 March, 2018.
Static timing analysis will be done on digital VLSI circuits to ensure that, paths within the designed module are not having timing violations in the form of setup and hold violations. In VLSI designs, optimization of entire design can be done for timing convergence. General techniques which can be applied in digital circuits for timing closure are explained here.
STA, timing convergence, clock tuning, timing closure, high speed VLSI designs
