Optimized architecture design of 2-D Mesh NoC with advanced technology results into low power consumption and it is further optimized with Power Compiler from SYNOPSIS using SAED 90 nm Technology. In this design of 2-D Mesh NoC, Power and Area optimization with Gate-Level Power Optimization, Power is obtained. Power is reduced by 77% and Area is reduced by 44%. Therefore Low Power Design Methodology used in this design resulted into improvement of Chip design significantly.
RTL Clock Gating, NoC, Gate Level Power Optimization, SAIF, ASIC
