B. Tech, Electronics and Communication Engineering, Geethanjali College of Engineering and Technology, Hyderabad, India
Online published on 31 March, 2018.
This paper presents a new architecture of Floating point Vedic Multiplier which operates on Vedic Mathematics called Vedic Sutras. It uses a method called Urdhav Tryakbhyam to multiply two mantissas in which kogge stone parallel prefix adder is used to add partial products. Vedic Mathematics is an emerging field where lot of research is going on Vedic mathematics and its implementation for engineering applications. Among all arithmetic operations like addition, subtraction, multiplication and division, multiplication takes longer time for computation. So this paper is focused on reduction of delay and number of LUT's when compared to conventional multipliers. The Architecture is implemented using Xilinx Vertex 6 FPGA and the results indicate that the proposed Multiplier is very efficient in terms of speed when compared to decimal multipliers implemented with direct manipulation of floating point formats. It has been observed that improvement in speed is about 1.05 times on Vedic multipliers which is suitable for Digital signal processing applications.
Floating point Multiplier, Urdhav Triyakbhyam, Kogge stone Adder
