Performance analysis of XOR/XNOR circuits using VTMOS and reversible logic

Power consumption, delay and area are the main considerations in VLSI systems. The prime motive of this work is to design a low power and high speed circuit with desired performance and diverse range of applications. The rapid growth of portable electronic devices emphasizes the need for energy and area efficient design to attract the end users. The exclusive OR (XOR) and exclusive NOR (XNOR) are the basic building blocks of many arithmetic and logic circuits like comparators, adders, linear shifters, crypto processors. The performance of the complex logic circuit is affected by the individual XOR/XNOR modules, therefore careful design is needed to obtain full voltage swing, less power consumption and delay. Here we focused on VTMOS logic for optimization. All circuits are simulated in HSPICE 130nm CMOS technology. The simulation results demonstrate that VTMOS exhibit less transistor count, decreased delay by 51.31%. Also compared reversible and irreversible logic for checking signal integrity. On an average, circuits with reversible logic exhibits 49.8% improvement in delay and 48.3% improvement in PDP.