Procedure for Verification and Testing of Critical Functionalities for an IP Core Under Reset Condition

Involvement for an intellectual property (IP) core assessment demonstrates diverse methodologies that can be implement for utilization of IP-core in CEH (Complex Electronic Hardware) andthese should reflect to design level at which IPis conveyed(soft, firm, hard) and basically remindson the availability to thedesigndata. Using an IP-coreorutilizing inside the airborne electronic hardware, the IP user ought to pick the most suitable approaches to assuring that the IP will satisfy the designaffirmationgoals. This papergivesdata on the methodologies that can be utilized, or the testing of IP core as per DO-254 measurements and these measurements how to verify in to possible condition like reset scenario to verify critical module or functionalities under hardware requirements. The main objective of this paper is the Target level testing of IP CORE, it will be analyzed by capturing and verifying the data, whether transmitted data contains proper values by the use of analyzer tool. The efficacy of the data is demonstrated with graphic controller as a case study.