Journal of Innovation in Electronics and Communication Engineering
  • Year: 2018
  • Volume: 8
  • Issue: 2

Implementation of High Speed and Efficient 1-Bit Full Adder and its Performance Analysis

  • Author:
  • S Rahul, C H Mohan Babu
  • Total Page Count: 5
  • Page Number: 39 to 43

Department of Electronics and Communication Engineering, Bharat Institute of Engineering & Technology, Mangalalpally, India

*mohaniitkgp08@gmail.com

Online published on 7 October, 2019.

Abstract

The most basic computational process found in systems of digital in binary addition, to establish this method binary adders are used, half adder and full adders are usually often used to perform out binary addition. This paper gives a compression of different design of 1 bit full adde rwith respect to number of transistors/gate count, power and power delay product.

Keywords

Half adder-Full adder, PMOS-CMOS, TG, GDI, GDI-PTL, Number of transistors/Gate Count, Delay, Power and PDP