Journal of Innovation in Electronics and Communication Engineering
  • Year: 2019
  • Volume: 9
  • Issue: 2

Designing Various 64-bit Adders using VHDL in VIVADO

  • Author:
  • Konda Sai Prakash Reddy
  • Total Page Count: 6
  • Page Number: 6 to 11

Department of Electrical and Computer Engineering, University of Victoria, Canada, skonda@uvic.ca

Online published on 4 March, 2020.

Abstract

Addition is considered to be the most fundamental and important operation in the field of digital design. Adders are basic building blocks for designing Subtractors, Multipliers etc., They are also used in Processor design, i.e. for designing ALUs, CPUs and GPUs etc.

In this work, I will be designing five different 64-bit adders considering various design constraints. One among those will be a general 64-bit Ripple Carry Adder, designed for the sake of comparing other adders. Other four adders are Carry Look Ahead Adders with different design specifications.

Keywords

Ripple Carry Adder, Carry Look Ahead Adder, Timing Constraints, C_in (Carry in), C_out (Carry out), VHDL, Vivado