A 16×16 MUX Based Multiplier Design Using Optimized Static CMOS Logic Style

Simpler VLSI implementation of array multipliers makes them preferable for smaller operand sizes, in-spite of their linear time complexity. In general array multipliers have bad space complexity O (n²), and it requires approximately n² cells to produce multiplication, therefore as the operand size grows the circuit takes large area and power. In this paper we present a MUX based 16×16 unsigned multiplier circuit, which utilize an efficient partial product generation and partial product addition technique. The time and space complexity of such multiplier is much better than simpler array multiplier techniques. The multiplier has been designed using optimized static CMOS logic cells to provide best area, power and delay performance. The multiplier circuit is implemented using conventional CMOS logic in 0.6μm, N-well CMOS process (SCN_SUBM, lambda=0.3) of MOSIS, and simulated after parasitic extraction. The simulation result shows large reduction in propagation delay and the average power compared to tree multiplier implementation by [3].