Design of a CMOS Comparator for Low Power and High Speed

This paper reports comparator design for low power & high speed. The present Design is specially design for high resolution Sigma Delta Analog to Digital Converters (SDADCs). Design is based on two stage CMOS OP-AMP technique. Simulation results have been obtained by 0.5 micron technology, considering ±2.5 supply voltage & 2.5 V Input range. Design has been carried out in Tanner tool using HP 0.5 micron technology. Simulation results are verified using S-Edit and W-Edit. We have achieved the propagation delay (speed) of 3.6 nano sec. with low power consumption about 0.31 mW. Finally, compare the proposed results with earlier work done [5], [10] and get improvement in presented results.