Low Power and High Speed CMOS Comparator Design Using 0.18μm Technology

This paper presents a design of a CMOS comparator with a preamplifier regeneration circuit. Design has specially concentrated on low power dissipation, high speed, and low propagation delay. For the performance verification, the design was simulated in 0.18μm CMOS Technology. We have compared the results of present design with earlier reported work and obtained improvement in the present results. This Design have obtained power dissipation 132.7μW, speed 100MHz, Propogation delay of 0.14μs, slew rate 72.14 v/μs, settling time 3.07μs respectively.