Simulation and synthesis of efficient majority logic fault detector using EG-LDPC codes to reduce access time for memory applications

This paper presents an error-detection method for Euclidean Geometry low density parity check codes with majority logic decoding methodology in VHDL language and the output is verified with the help of Xilinx12.1. Majority logic decodable codes are suitable for memory applications due to their capability to correct a large number of errors. However, they require a large decoding time that impacts memory performance. The proposed fault-detection method significantly reduces memory access time when there is no error in the data read. The technique uses the majority logic decoder itself to detect failures, which makes the area overhead minimal and keeps the extra power consumption low. Starting from the original design of the ML decoder introduced, the proposed ML Detector/Decoder (MLDD) has been implemented using the Euclidean Geometry low density parity check codes. The proposed improved majority logic detector/decoder to perform data error correction in simple way using additional error correction technique and also reducing the delay time by detecting the errors in parallel manner. Hence the decoding process uses less number of cycles which reduces the delay.