International Journal of Engineering and Management Research
  • Year: 2026
  • Volume: 15
  • Issue: 2

Design and Implementation of AHB to APB Bridge using Verilog

  • Author:
  • PS Bellerimath1*, S Shirakol2, LV Gunari3, N Rachana4, SP Mahat5, C Arali6
  • Total Page Count: 5
  • Page Number: 199 to 203

1Preeti S Bellerimath, Assistant Professor, Department of Electronics and Communication Engineering, SDM College of Engineering and Technology, Dharwad, Karnataka, India.

2Shrikanth Shirakol, Assistant Professor, Department of Electronics and Communication Engineering, SDM College of Engineering and Technology, Dharwad, Karnataka, India.

3Laxmi Vadiraj Gunari, Student, Department of Electronics and Communication Engineering, SDM College of Engineering and Technology, Dharwad, Karnataka, India.

4N Rachana, Student, Department of Electronics and Communication Engineering, SDM College of Engineering and Technology, Dharwad, Karnataka, India.

5Sahil P Mahat, Student, Department of Electronics and Communication Engineering, SDM College of Engineering and Technology, Dharwad, Karnataka, India.

6Chirag Arali, Student, Department of Electronics and Communication Engineering, SDM College of Engineering and Technology, Dharwad, Karnataka, India.

*Corresponding Author Preeti S Bellerimath, Assistant Professor, Department of Electronics and Communication Engineering, SDM College of Engineering and Technology, Dharwad, Karnataka, India. Email: prtbellerimath69@gmail.com

Abstract

Efficient on-chip communication is vital in modern embedded and System-on-Chip (SoC)architectures. This project presents the design and implementation of an AHB (Advanced High-performance Bus) to APB (Advanced Peripheral Bus) bridge using Verilog Hardware DescriptionLanguage (HDL). The bridge serves as an interface between high-speed AHB masters and low-speedAPB peripherals, with a Finite State Machine (FSM) governing the control flow—including addressdecoding, data transfer, and handshake signal management. The Verilog-based design emphasizesmodularity, timing accuracy, and hardware compatibility, making it well-suited for both FPGA prototyping and ASIC integration. Functional simulation and synthesis validate the bridge’s correctness, performance, and efficient resource utilization. The FSM-based control ensurespredictable and reliable communication across the AHB and APB domains, fulfilling the structuredconnectivity demands of AMBA-based SoC designs [1].

Keywords

Verilog HDL, FSM, AHB to APB Bridge, SoC Communication, AMBA Protocol, Embedded Systems, Bus Interface, FPGA, Data Transfer