Design of High Performance Floating Point SRT Divider Using Divisor and Partial Remainders Estimates

SRT dividers are common in modern floating point units. Higher division performance is achieved by retiring more quotient bits in each cycle. Previous research has shown that realistic stages are limited to radix-2 and radix-4. Higher radix dividers are therefore formed by a combination of lowradix stages. In this paper, we present an analysis of the n-bit divider and Comparative analysis of different dividers in case of delays and performance. We show the performance and area results for a wide variety of divider architectures and implementations. We conclude that divider performance is only weakly sensitive to reasonable choices of architecture but significantly improved by restoring and non restoring techniques.