Modelling of Hybrid CMOS-SET based Highly Efficient Parallel-In Serial-Out Shift Register for Next Generation Electronics

Single electronics, a comparatively new field of solid state science and technology, has been developed speedily in both theory and experiments because the essential e-beam lithography techniques have matured enough during the past two decades. Research in this field ushered promising domino effect for near future. In spite of numerous advantages, the fragility in fully exploring the properties of Single Electronic Transistors (SET) and further manipulating them in new architectures by which they can be integrated on a single chip remains a challenge. But thereafter, un-put-down-able device scientists then articulated hybridization of existing CMOS technology with SETs to overcome the specific drawbacks of SET and to explore new horizon in device research. Here a similar attempt to realize hybrid CMOS-SET based Parallel-In-Serial-Out Shift Register is revealed to investigate the robustness and fastness of the novel architecture by comparing it with existing CMOS technology. The consequences besides being impressive bears better validation to incorporate the model in near future.