International Journal of Engineering and Management Research (IJEMR)
  • Year: 2014
  • Volume: 4
  • Issue: 3

A High Speed Transmission Gate Logic Base 1/N Frequency Divider Digital Parallel Counter Design

  • Author:
  • Amreen Parveen, Subhasis Bose, Sachin Bandewar
  • Total Page Count: 3
  • Page Number: 132 to 134

Department of Electronics and communication, RKDF University, Bhopal, Madhya Pradesh, India

Online published on 21 November, 2017.

Abstract

Flip-flops are the essential building blocks of any counter circuit. In our design counter consist of a layout design of transmission gate base latch circuit connected in master slave arrangement In this paper we design a frequency divider counter design by pass transistor logic circuit technique. Transmission gate can be act as a switch with low resistance and capacitance having the ratio less logic and the DC characteristic of this gate are independent of the input levels. The proposed counter is a 3 bit pass transistor base counter, which chain through a fixed set of pre assigned count states, of which each next count state represents the next counter value in sequence. The counter frequency to a great extent improved by sinking the gate count on all timing paths to two gates using pass transistor circuit design techniques. In our work the counter working frequency is improved by using a parallel counter architecture of pass transistor base flip-flops. This is proceeded to remove the carry chain delay and decrease AND gate fan-in and fan-out. The proposed counter is design for low-power and high-speed applications. The design can be implemented using MICROWIND.

Keywords

Architecture design, parallel counters design