1Department of Electronics and Communication Engineering, Meri college of Engineering & Technology, Sampla, Bhadurgarh, Haryana, India
2Assistant Professor, Department of Electronics and Communication Engineering, Meri college of Engineering & Technology, Sampla, Bhadurgarh, Haryana, India
Online published on 21 November, 2017.
Multiplication is one of the basic functions used in digital signal processing (DSP). Hardware resources and processing time required by it are more than addition and subtraction. There are two kinds of multiplication algorithms, serial multiplication algorithms and parallel Multiplication algorithms. Serial multiplication algorithms use sequential circuits with feedbacks. Parallel multiplication algorithms often use combinational circuits, and do not contain feedback structures. This paper presents various multiplier architectures. Multiplier architectures fall generally into two categories i.e., “tree” multipliers and “array” multipliers. Tree multipliers add as many partial products in parallel as possible and therefore, are very high performance architectures. Multiplication operation involves generation of partial products and their accumulation. The speed of multiplication can be increased by reducing the number of partial products.
Architecture, Digital system, Hardware, Logic functions, Propagation delay, Sequentially
