1Department of Electronics and Communication Engineering, Meri college of Engineering & Technology, Sampla, Bhadurgarh, Haryana, India
2Assistant Professor, Department of Electronics and Communication Engineering, Meri college of Engineering & Technology, Sampla, Bhadurgarh, Haryana, India
The multiplication operation is an integral part of any digital system or digital computer, most notably in signal processing, graphics and scientific computation. It requires more hardware resources and processing time than addition and subtraction. In fact, 8.72% of all instructions in a typical processing unit is multiplier. The speed of the system depends upon speed of the multiplier to a large extent. This necessitates the need of a high speed multiplier. With the advancement in technology, various techniques have been proposed to design multipliers, which offer high speed, low power consumption and lesser area. Thus making them suitable for various high speed, low power compact VLSI implementations. This paper presents a novel design of a high-speed Hybrid Wallace tree multiplier.
Array, Architecture, Digital, Mathematical, Multiplication, Parallel, Serial, Wallace
