Design & Comparative Analysis of Dynamic Decoder and Tree Decoder

The key objective of this project is to design a decoder which can be used for hardware purpose. A decoder is a combinational circuit that converts binary information from n input lines to a maximum of m=2ⁿ output lines. In this paper are design of Dynamic decoder and Tree Decoder. Also shows a comparative analysis of tree decoder with corresponding dynamic decoder and tree decoder highlights the benefits of preferring tree decoders in digital system designs. Large tree decoder can be constructed by reusing smaller similar sub-modules. Thus the structure is symmetric. The symmetric and regular structure of tree decoder makes the system easy to design. The structure obeys regularity and modularity concepts of VLSI circuit. Digital communication systems have proven their efficiency and brought a new element in the chain of signal transmitting and receiving, the digital processor.

The design to be implementing by using Verilog-HDL language. The Simulation and Synthesis by using ISE Xilinx 13.4 tool.