SHA-1(Secure Hash Algorithm) is iterative, one-way hash functions that can process a message to produce a condensed representation called a message digest. This algorithm enable the determination of a message's integrity: any change to the message will, with a very high probability, results in a different message digest. This property is useful in the generation and verification of digital signatures and message authentication codes, and in the generation of random numbers (bits). SHA-1 can be described in two stages: pre-processing and hash computation. ASIC (Application Specific Integrated Circuit) implementation of SHA-1 Algorithm on FPGA using combinational logic.
i. Verilog Coding using Modelsim.
ii. Synthesize SHA-1 on Xilinx-ISE tool using target technology.
iii. Implementation on FPGA
