International Journal of Engineering and Management Research (IJEMR)
  • Year: 2014
  • Volume: 4
  • Issue: 3

Designing Field Programmable Gate Array

  • Author:
  • Neetu 1, Sachin Kumar2
  • Total Page Count: 6
  • Page Number: 377 to 382

1Department of ECE, Meri College of Engineering & Technology, Sampla, Haryana, India

2Assistant Professor, Department of ECE, Meri College of Engineering & Technology, Sampla, Haryana, India

Online published on 21 November, 2017.

Abstract

This algorithm enable the determination of a message's integrity: any change to the message will, with a very high probability, results in a different message digest. This property is useful in the generation and verification of digital signatures and message authentication codes, and in the generation of random numbers (bits). ASIC (Application Specific Integrated Circuit) implementation of FPGA using combinational logic.

i. Verilog Coding using Modelsim.