Design & Implementation of 6 to 64 Line Decoder

The objective is to design a 6 to 64 line decoder which can be used for hardware purpose. A decoder is a combinational circuit that converts binary information from n input lines to a maximum of m=2ⁿ output lines. In this paper are design of different types of 6 to 64 line Decoders. Also shows a comparative analysis in different types of decoder in terms of 4 Inputs LUTs, Total Memory Usage, no of Slice & Combinational Path Delay in digital system designs. The Structures made here are hardware synthesizable on FPGA board and are done in a respective manner. The decoder implemented here offers to new radio equipment, the flexibility of a programmable system. The design to be implementing by using hardware description language. The Simulation and Synthesis by using ISE Xilinx 13.4 tool