Design and Implementation of Arbitrary Modulo-Set RNS Forward Converters on FPGA

In this paper we analyzed four different architectures, which uses combinational logic along with memory (LUTs). The first architecture is purely sequential conversion. Second architecture is combination of sequential and parallel. The third architecture is the modified version of second architecture and final architecture is purely parallel. Architecture-3 utilizes 50% less resources when compared to architecture 1 & 2. Architecture-3 is 3 times faster than Architecture 1. This paper has designed and implemented forward converter architectures and performs the area, speed. Verilog HDL is used for coding. Implementation of different architecture has been done on XILINX VERTEX 5XC5VLX110T-2FF1136 OPEN SPARC board. It is been identified that modified sequential/parallel approach has better performance in speed and area when compared with other architectures.