Design and Implementation of High Radix Booth Multiplier using Koggestone Adder and Carry Select Adder

This paper presents the design and implementation of radix-16 booth Multiplier. The number of partialproducts are reduced to n/3 in radix-8. We can reduce the number of partial products even further to n/4 by using a higher radix16 in the multiplier encoding, thereby obtaining a simpler CSA tree. This implies less delay and a smaller area size. Since this multiplication operation is for both signed and unsigned numbers, cost of the system can also be reduced. The carry select adder (CSA) tree and the final adder can speed up the operation of multiplier. Koggestone adder is a parallel prefix form carry look ahead adder. We determine that by replacing carry select adder(CSA) and final two operand parallel prefix adder with parallel prefix adders of koggestone algorithm reduces delay further more resulting in substantial increase in speed of circuits. Since signed and unsigned multiplication operation is performed by the same multiplier unit the required hardware and the chip area reduces and this in turn reduces power dissipation and cost of a system.