Design of High Speed Modified Booth Algorithm MAC using RCA and CLAA

This paper focused on a combined process of multiplication and accumulation based on radix-16 both encodings. In this Paper, we investigate the method of implementing the Parallel MAC with the smallest possible delay. Parallel MAC is frequently used in digital signal processingand video/graphics applications. A new architecture of multiplier-and accumulator (MAC) for highspeed arithmetic. By combining multiplication with accumulation and devising a hybrid type of carry Ripple Carry Adder and Carry Look Ahead Adder (RCA And CLAA), the performance was improved. Since the accumulator that has the largest delay in MAC was merged into Adders, the overall performance was elevated. The MAC provides high speed multiplication and multiplication with accumulative addition. Enhancing the sped of operation of the parallel MAC is a major design issue. Modified Booth's algorithm (MBA) and has the modified array for the sign extension in order to increase the bit density of the operands. The Adder propagates the caries to the least significant bits of the partial products and generates the least significant bits in advance to decrease the number of the input bits of the final adder. Also, the proposed MAC accumulates the intermediate results in the type of sum and carry bits instead of the output of the final adder, which made it possible to optimize the pipeline scheme to improve the performance. The proposed architecture was synthesized with 250, 180 and 130 m, and 90 nm standard CMOS library.