A Hybrid Multiplier which is made up by using advantages of modified Booth Algorithm and Wallace Tree multiplier to speed up the multiplication is implemented. Hybrid Multiplier speed can be increased by reducing the number of partial product and using parallel addition. In Hybrid Multiplier Partial Product are generated using modified booth algorithm which reduces the number of partial products and Wallace tree architecture is used for addition to increase the overall multiplication speed and at final stage Carry Select Adder(CSA) is used to generate final output product. The CSA divides the words to be added into blocks and forms two sums for each block in parallel, one time with the assumption of the carry being zero and the other assuming one. The design is using Verilog HDL code and synthesis by using the Xilinx ISE 13.4 software and implementation on Spartan3E-FPG.I will show design summary of my result in terms of FPGA parameters like LUTs, Number of Slice, Combinational Path Delay, and Number of bonded BOIs.
Radix-4 Booth Multiplier, Carry Select Adder(CSA), Multiplier(MR), Multiplicand(MD), Verilog-HDLs
