Design & Implementation of Vedic Multiplier on FPGA

This paper projected the design of high speed Vedic Multiplier by the techniques of Ancient Indian Vedic Mathematics that have been customized to get betterperformance. Vedic Mathematics be the ancient scheme of mathematics which has a sole technique of calculations based on 16 Sutras. The work has proved the effectiveness of Urdhva Triyagbhyam-Vedic method for multiplication which strikes a distinctionduring the real process of multiplication itself. Urdhvatiryakbhyam Sutra is most resourceful Sutra, giving minimum delay for multiplication of all types of numbers. Further, the Verilog HDL coding of Urdhvatiryakbhyam Sutra for 16x16 bits multiplication and their FPGA implementation by Xilinx10.1 and MODELSIM 6.4a software's on Spartan 3E kit have been done. The synthesis results show that the path delay for calculating the product of 16x16 bits is24.906 ns. When Vedic Multiplier is compared with classical Vedic multipliers it is advantageous in each aspect. The study reveals that Vedic multiplier has least path delay when compared with its other peer existing multipliers structures.