Design of Reconfigurable Adder Architecture for FPGA

The objective of this thesis is to design a reconfigurable adder that does fast addition operation. The architecture of the adder is such that it should add two operands fast. The reconfigurable adder is then implementing on FPGA, Spartan 3E series board. The adder is also analysed for ASIC design to better understand the adder design for performance & area. There are many cases where it is desired to add more than two numbers together. The straightforward way of adding together m numbers (all n bits wide) is to add the first two, then add that sum to the next, and so on. This project covers different aspects of adder that perform fast addition & it also explained reconfigurable architecture of FPGA for reconfigurable design. So, having said that in future the adder can be deploy for FPGA purposes or the design can be treated as IP core for ASIC designs. Project module will design by very high speed integrated circuit hardware descriptive language (VHSIC-HDL) Simulation by Model-Sim 6.4c Software tool and Synthesis by ISE-Xilinx 13.4 software tool.