Design Architecture of Modified Radix-4 Booth Multiplier

Multiplication is an essential basic function in arithmetic operations. The multiplication dominates the execution time of most DSP algorithms, so there should be a need of high speed multipliers. Multiplication time is still the leading factor for determining the instruction cycle time of a DSP chip. The multiplication operation is an integral part of any digital system or digital computer, most notably in signal processing, graphics and scientific computation. It requires more hardware resources and processing time than addition and subtraction. The speed of the system depends upon speed of the multiplier to a large extent. This necessitates the need of a high speed multiplier. A Modified Radix-4 booth Encoder Multiplier which is made up by using advantages of modified Booth Algorithm and Tree multiplier to speed up the multiplication is implemented. Radix-4 Multiplier speed can be increased by reducing the number of partial product and using parallel addition. In Radix-4 booth Encoder Partial Product are generated using modified booth algorithm which reduces the number of partial products and Tree architecture is used for addition to increase the overall multiplication speed and at final stage Carry Select Adder (CSA) is used to generate final output product. The design is implemented using Verilog HDL code and successfully implemented by using the Xilinx ISE 13.4 software. The experimental results indicate that Radix-4 multiplier provide 78.41% increase in speed compare to array multiplier.