Design and Implementation of Distributed Canny Edge Detector on FPGA

In this project, we present a distributed Canny edge detection algorithm that results in significantly reduced memory requirements decreased latency and increased throughput with no loss in edge detection performance as compared to the original canny algorithm. The new algorithm uses a low-complexity 8-bin non-uniform gradient magnitude histogram to compute block-based hysteresis thresholds that are used by the canny edge detector. Furthermore, FPGA-based hardware architecture of our proposed algorithm is presented in this paper and the architecture is synthesized on the Xilinx Spartan 3 FPGA. The design development is done in VHDL and simulates the results in modelsim 6.3 using Xilinx 12.2.