International Journal of Engineering and Management Research (IJEMR)
  • Year: 2015
  • Volume: 5
  • Issue: 4

A Literature Review and Over View of Built in Self Testing in VLSI

  • Author:
  • Jalpa Joshi1, Jaikaran Singh2
  • Total Page Count: 5
  • Page Number: 390 to 394

1Electronics & Communication. VLSI, SSSIST, Sehore, India

2Electronics and Communication, SSSIST, Sehore, India

Online published on 21 November, 2017.

Abstract

Now a day due to the technology advancement the number of component on a single chip is increased and that's why complexity of the circuit is also increased day by day. Due to this the problem of fault is also increased. So detection and elimination of the faults in very large scale integrated system (VLSI) is the major factor. For the analysis of fault we have required “Testing”. Testing is process in which we have testing the circuit improve the fault tolerance in circuits. In the last decade there are different have been introduced for testing here in the paper we focused one of the most famous technique that is the built in self testing (BIST). Built in self testing is technique that is used different circuit testing. There are many improvement in the field of BIST. So in this we have to the working phenomena of BIST, and its different technique also with the application of BIST. The main focus is done on BIST, online and offline method of detection and elimination of faults.

Keywords

BIST, VLSI, UART, Testing, Circuit fault