Embedded Logic Flip-Flops: A Conceptual Review

With advancement in CMOS technology, a lot of research has been done to develop various logic styles to improve the performance of logic circuits. D flip-flops (DFF) are fundamental building blocks in almost every sequential logic circuit. Hence, in sequential logic circuits, the overall performance of the circuit is affected by the performance of constituent DFFs.

In recent years, the focus has been towards incorporating higher clock rates in a processor for better performance. To achieve high clock rates, fine granularity pipelining techniques are used, which implies that there are relatively a fewer levels of logic in each pipeline stage. A major consequence of this design trend is that the pipeline overhead has becoming more significant. The primary cause of pipeline overhead is the latency of the flip-flop or latch used to design the processor and the clock skew of the system. This calls out for the need of incorporating the logic functionality within the architecture of flip-flop. The new family of flipflops are called Embedded Logic Flip Flops. In this Paper, we have reviewed various Flip-flop architectures which have been proposed so far. Our attempt is to do a qualitative analysis and comparison of the proposed Embedded logic flip-flop designs.