An Efficient Implementation of 32 bit Binary Multiplier for High Speed Design Applications

The Binary Multiplication is one of the crucial operation in high power computing applications where performance is determined by the speed of multiplier used. So high speed multiplier play important role in any digital design, dsp processor and general processor. Here an attempt is made to build efficient fast 32 bit binary multiplier compared to the existing ones like booth and vedic algorithm based multiplier. In term of speed the proposed method is much efficient. Hardware implementation is done on VERTEX-5 Coding is done in Verilog HDL.