Design and Synthesis of Systolic Array Architecture for Matrix Multiplication

In most of the signal and image processing applications, matrix multiplication plays very important role. It is the very basic operation used in so many DSP applications. Through This paper an effective design for the Matrix Multiplication is demonstrated using Systolic Architecture. Here the comput ing speed is increased by the use of pipelining and parallel processing together as a single concept. Here, the code is written for matrix multiplication without systolic architecture and matrix multiplication with systolic architecture in Verilog HDL, compiled and simulated by using Xilinx ISE 14.2i and targeted to the device xc3s500e-5-ft256 then finally the designs are compared to each other to evaluate the performance of proposed architecture. In the proposed Matrix Multiplication with systolic architecture vedic multiplier is used to speed up the computation speed.