The 32bit RISC MIPS processor has five pipeline stages. It is designed with Verilog HDL, simulated using Xilinx 14.2 and implemented on Spartan 6 Digilent Board. Now days it important to build the product with high processing speed, low power consumption and less area. The 32bit processor executes instruction in single cycle, uses very less amount of lookup tables of Spartan 6. In this paper a technique of pipeline represents to speed up the processor. Proposed approach has been compared with existing approach in terms of area, speed, power consumption.
RISC, MIPS, Spartan 6, FPGA, Xilinx14.2, SOC
