An Efficient Constant Multiplier Architecture Based On Vertical-Horizontal Binary Common Sub-Expression Elimination Algorithm

Constant multiplier is a preliminary unit of FIR filter which serves the purpose of multiplying the input with set of coefficients to get desired filter response. High performance DSP systems are implemented in custom hardware, in which the designer has the ability to choose which logic elements will be used to perform the computation. By exploiting the properties of binary multiplication, it is possible to realize constant multiplication with fewer logic resources than required by a generic multiplier.

In this thesis, a thorough analysis of the existing algorithms, the underlying frameworks, and the associated properties is provided. This project based on vertical-horizontal binary common sub-expression elimination

In this thesis, a thorough analysis of the existing algorithms, the underlying frameworks, and the associated properties is provided. This project based on vertical-horizontal binary common sub-expression elimination (VHBCSE) algorithm attempt to address the weaknesses of the existing fixed bit algorithms such as 2-bit and 3-bit binary common sub-expression algorithms. We also included new strategies which are fundamentally different from the existing methods. Binary common sub-expression elimination algorithms are known to be very efficient in reducing the number of logical operations that are to be performed in constant multiplication there by accelerating the speed of chip as well as reducing power consumption. It is also efficient in reducing the number of adder cells required for the computations.