Compressors Based High Speed 8 Bit Multipliers Using Urdhava Tiryakbhyam Method

Arithmetic operations are becoming a bigger concern in the digital system for applications like ALU (Arithmetic and Logic Unit) and DSP (Digital Signal Processing). Our work focuses on novel 4: 2 and 5: 2 Compressors(CM)applied in multiplication architectures such as Unsigned Wallace tree multiplier, Vedic mathematics using Urdhva Tiryakbhyam sutra, and Wallace tree multiplier, Signed Booth multipliers. The proposed compressors architectures have shown better results when compared with the existing compressors. In our project, a design of 8-bit x 8-bit signed multipliers for high speed Digital Signal Processing (DSP)applications was done. Urdhava Tiryakbhyam method is used in the architecture of multipliers to implement high speed and it also has less power consumption and delay. Our proposed work was compared with booth, array and Wallace multiplier in terms of area, delay and power consumption. Our techniques produces better result than the existing multipliers.