VLSI Implementation of Digital Down Converter (DDC)

A fundamental part of many communications systems is Digital Down Conversion (DDC). To optimize the conventional DDC (Single stage FIR filter) with respect to hardware Complexity, Speed, Power dissipation, Multi stage FIR filter approach is used which is more efficient. The aim of the project is to implement Digital Down Converter (DDC) on FPGA device efficiently. The received IF signal is down converted to base band level using DDC. The technique greatly reduces the amount of effort required for subsequent processing of the signal without loss of any of the information carried. DDCs implemented on FPGA have more flexible frequency and phase characteristics and higher precision computation. DDC will be implemented with above advantages on Xilinx FPGA. Results are analyzed using xilinx Analyzer.