Implementation of Efficient 5: 3 & 7: 3 Compressors for High Speed and Low-Power Operations

This paper demonstrate high speed and low-power compressors (5: 3 and 7: 3) for efficient parallel multipliers in Digital Signal Processing (DSP), simulated with Tanner EDA Tools. This is achieved by rapid critical path reduction than the conventional compressors. Though conventional 5: 3 compressor need four steps to reduce bits from 5 to 3, the used 5: 3 requires only 2 steps. For the investigation of overall performance of the simulated compressors in terms of delay and energy consumption; power, delay and power delay product (PDP) of the compressors are being analyzed.