International Journal of Engineering and Management Research (IJEMR)
  • Year: 2018
  • Volume: 8
  • Issue: 1

Low Power and Simple Implementation of Secure Hashing Algorithm (SHA-2) using VHDL Implemented on FPGA of SHA-224/256 Core

  • Author:
  • Dipti Thakur1,, Utsav Malviya2
  • Total Page Count: 4
  • Page Number: 1 to 4

1M Tech (Embedded System and VLSI Design), Gyan Ganga Institute of Science and Technology, Jabalpur, India

2Department of Electronics and Communication, Gyan Ganga Institute of Science and Technology, Jabalpur, India

*Corresponding Author: deeptithakuroec@gmail.com

Online published on 14 May, 2018.

Abstract

Cryptography plays an important role in the security of data. Even though the data is encrypted it can be altered while transmitting on the network so data should be verified using a digital signature. Hashing algorithms are used to create these digital signatures for verification of the data received. Hashing algorithm like Secure Hash Algorithm-2 (SHA-2(224/256)) is designed which has a fixed output length of 512-bits.

Then to improve on power a low-power technique such as latch based clock gating technique is used. After applying these techniques all the designs are compared in terms of power, delay and frequency

Keywords

Data Encryption, RPT, Hashing