EM1 noise reduction is generally accomplished by three means: suppression of noise source, isolation of noise coupling path, and filter shielding. In this paper, another means of EMI noise reduction is proposed is Simultaneous switching noise (SSN) has become an important issue for generation of EMI effect in the design of the internal on chip power distribution networks in current very large scale integration/ultra large scale integration circuits. An inductive model is used to characterize the power supply rails when a transient current is generated by simultaneously switching the on-chip registers and logic gates in a synchronous CMOS VLSI/ULSI circuit. An analytical expression characterizing the SSN voltage is presented here based on a lumped inductiveresistive-capacitive model. The peak value of the SSN voltage based on this analytical expression is within 10% as compared to SPICE simulations. Design constraints at both the circuit and layout levels are also discussed based on minimizing the effects of the peak value of the SSN voltage.
Integrated circuit interconnection, on-chip inductance, power distribution network, simultaneous switching noise
