International Journal of Engineering Research
  • Year: 2016
  • Volume: 5
  • Issue: 8

Logarithmic Multiplier: An Analytical Review

  • Author:
  • Parvin Akhter, Sachin Bandewar, Durgesh Nandan
  • Total Page Count: 3
  • Page Number: 721 to 723

Department of Electronics and Communication Engineering, Sri Satya Sai College of Engineering (RKDF university), Bhopal, Madhya Pradesh, India

* parvin.akhter90@gmail.com

** sachin.bandewar9@gmail.com

*** prof.durgeshnandan@gmail.com

Online published on 9 March, 2017.

Abstract

In last four decades, the Logarithmic Number System (LNS) is the most vocative words in the field of arithmetic operations (like addition, subtraction, multiplication, and division). In all arithmetic operations multiplication is most area consuming component, but researchers have analyzed that, LNS has potential to solve this problem. Hence, this paper gives a detailed and meaningful discussion of the evolution of LNS, systematic developments of the LNS multiplier architecture design, highlights the research areas, a further possibility of improvements, their limitations and finally application in the various fields.

Keywords

Arithmetic circuits, antilogarithmic conversion, Operand decomposition, logarithmic conversion, logarithmic multiplication, logarithmic number system, Mitchell method