FPGA Implementation of Fast Redundant Adders Using Universal Logic

Redundant Binary Signed Digit Adder and Multiplier circuits are logic circuits and designed to perform high-speed arithmetic operations. RBSD Number System is not convenient for manual computations but useful in designing high-speed arithmetic machines. It is gaining popularity in computationally intensive environments due to possessing of the carry-free addition/subtraction properties. In RBSD number system carry propagation chains are eliminated which reduces the computational time substantially, thus enhancing the speed of the machine.

A new design of fast adder using universal logic is implemented and proposed in this paper. Fast RBSD adder cell, proposed by Kal and Rajshekhar in 1990 was further modified by Neelam Sharma in 2006. In this research paper this universal logic adder cell has been remodified for reducing circuit complexity and cost. Since the number of gates has been reduced per cell, implementation time has also reduced. Redundant logic has a high advantage when number of bits is increased that means 64, 128, 256 bit adders using this logic are highly appreciable than the logic which was being used previously. Since for subtraction, multiplication, and division operations the addition is the base, the RBSD addition proposed here is useful in construction of the entire ALU with fast processing speed and less circuit complexity.

One further advantage of the RBSD adder cell is that it has a simple design. The same architecture is used for the addition of any of n-bit. In contrast the CLA adder cell being used previously for high-speed addition is only successful for addition up to 12 bit numbers and when the number of bits are increased the circuit becomes very complex. Therefore CLA adders can't be used for the addition of higher bit length numbers.