A review on using asynchronous circuit design to reduce power consumption in a vlsi

A comparison with synchronous circuits suggests four opportunities for the application of asynchronous circuits: high performance, low power, improved noise and EMC properties, and a natural match with heterogeneous system timing. In this overview article each opportunity is reviewed in some detail, illustrated by examples, compared with synchronous alternatives, and accompanied by numerous pointers to the literature. This paper gives a diagram of fault models used to create tests for fabrication faults in VLSI circuits and a few results reported so far in the field of testing and design for testability of asynchronous VLSI circuits using previous studies.