*P.G Scholar, Electronics Communication Engineering, Sri Shakthi Institute of Engineering, Coimbatore
**Assistant Professor, Electronic Communication Engineering, Sri Shakthi Institute of Engineering, Coimbatore
Online published on 27 July, 2015.
Most of the Memory cells have been protected from soft errors; due to the increase in soft error rate in logic circuits, the encoder and decoder circuitry around the memory blocks have become susceptible to soft errors as well and must also be protected with effective error correction codes. The reliability and security of systems protected by linear codes largely depend on the accuracy of the expected error model. To avoid a high decoding complexity, the use of one step majority logic decodable codes was first proposed for memory applications. Majority logic decodable (MLD) codes are suitable for memory applications because of their capability to correct large number of errors. Here Euclidean Geometry Low-Density Parity-Check (EG-LDPC) codes are used for error correction, because of their fault-secure detector capability. The proposed Majority Logic Decoder/Detector (MLDD) itself detects failures which minimize area overhead and power consumption. The memory access time is also reduced when there is no error in the data read. The proposed algorithm is coded in VHDL and simulated using ModelSim and Xilinx ISE 8.1 is imulator. The results obtained are compared with the existing version of the technique.
