Design and Performance analysis of CMOS based 7T SRAM using BIST Architecture

Testing of VLSI components is the most time consuming and tedious work. Built in self test architecture provides capability of providing the testing with the advantage of having high fault coverage and high speed of testing. Offline and online tests are available in BIST scheme. The use of a static-RAM structure to store the relative locations of the vectors that reach the circuit inputs examined in the window. In the current technology, less area, high speed and low power consumption are the most needed factors. In any high speed circuits, Static Random Access Memories (SRAMs) has been most usually used information storage devices. In the proposed paper work, a concurrent BIST Architecture ave been used for monitoring the set of input vectors during the normal operation of SRAM. A low power consumption is made possible than the previously used system.